1. Field of the Invention
This invention relates generally to memory systems that employ DRAM, and more particularly to methods and systems for handling the refreshing of DRAM memory cells.
2. Description of the Related Art
A typical DRAM memory cell consists of an access transistor and a storage capacitor, with the access transistor connecting the storage capacitor to a bitline when switched on such that the capacitor stores the logic value placed on the bitline. Due to the tendency of a capacitor to lose its charge over time, DRAM memory cells must be periodically ‘refreshed’, which serves to maintain the value stored in each storage capacitor at its desired value. The amount of time that a cell can retain its logic value is referred to as its “data retention time”.
One trend in the development of memory cells is that the cells have been shrinking due to advancements in process technology and the demand for ever larger memory capacity. This necessarily results in a reduction in the sizes of the access transistor and storage capacitor, which can lead to several problems. For example, each access transistor exhibits leakage which acts to slowly drain stored charge from the storage capacitor. This leakage characteristic—and thus each cell's data retention time—varies from transistor to transistor; however, this variability increases as the size of the access transistors is reduced. Another problem is that a shrinking memory cell results in a smaller storage capacitor, and thus a reduced storage capacitance. This can also adversely affect the data retention time characteristics of the cells.
These problems combine to result in the number of ‘weak’ memory cells—i.e., cells that have a below-average data retention time—increasing as the cells become smaller. Since DRAM is refreshed on a periodic basis, the weak cells having retention times shorter than the refresh period may lose their stored values. One way of avoid this is to provide a number of redundant memory cells, which can be accessed via a mapping process that would typically be built into the DRAM. However, the redundant cells and mapping logic consume extra area within the DRAM, and the mapping process can increase the DRAM's access time; the amount of overhead required for this solution may be unacceptably high.